For data transmission it is important to have bus drivers and bus receivers that allow devices to communicate quickly, efficiently and accurately. This data transmission may occur within a computer system, between computer systems, over a local or wide area network, or over other long distance networks.
One common technique for implementation of data transmission within a computer bus uses differential signaling technology to communicate between devices in a computer system. For communication of one signal, differential signaling may use two differential printed circuit board traces, two lines within a balanced cable, or two electrical routes within a semiconductor device. A variety of differential signaling standards exist, such as Low Voltage Differential Signaling (LVDS), High Voltage Differential Signaling (HVDS) and others. Of course, such differential signaling may also be used for other long-distance data transmission.
Typically, a differential driver includes a current source that drives one of the differential pair lines. The differential receiver has a high DC impedance, so that the majority of driver current flows across a termination resistor generating a voltage drop across the receiver input. When the driver switches, it changes the direction of current flow across the resistor, thereby creating a valid "one" or "zero" logic state.
To help ensure reliability, differential receivers may have a fail-safe feature that guarantees the output to be in a known logic state under certain fault positions. These fault conditions include open, shorted, or terminated receiver input. If the driver looses power, is disabled or is removed from the line while the receiver stays on with inputs terminated, the receiver output remains in a known state with the fail-safe feature. Without the fail-safe feature, if a fault condition occurred external noise above the receiver threshold could trigger the output and cause an error. A receiver without the fail-safe feature could even go into oscillation under certain fault conditions. The fail-safe feature ensures that the receiver output will be a HIGH--rather than in an unknown state --under various fault conditions. The fail-safe feature may be implemented with internal resistors that provide a DC offset of approximately 10 to 30 mV in the receiver circuit.
However, this internal fail-safe circuitry is designed to source/sink a small amount of current providing fail-safe protection for floating receiver input, shorted receiver input, and terminated receiver input, and is not designed to provide fail-safe in noisy environments when the driver is in a tri-state condition. If the cable picks up more differential noise than the internal fail-safe circuitry can overcome, the receiver may switch or oscillate. If this tri-state condition occurs, it is often recommended to add external fail-safe resistors to create a larger noise margin.
These external fail-safe resistors produce a voltage bias (a DC offset) and are useful in achieving a known state for a bus line when that bus line is not being driven, such as being in the tri-state condition described above. For example, data bus structures used in multi-point applications must ensure that when the bus is not driven (such as during no activity or during control activity) that receivers on the bus receive a negated state. This negated state is typically achieved by biasing the bus with a DC offset that assures that the receiver will indicate a non-asserted condition when that bus line is not being driven.
For example, a Small Computer System Interface (SCSI) bus uses a voltage bias in the termination at each end of the SCSI bus. The termination voltage bias is used during the arbitration phase of SCSI protocol in order to help determine which devices are asserting which bits on the bus. The voltage bias assures that any non-driven data lines are put into a negated state. When one peripheral asserts a data line, all of the other data lines will be in a negated state and it may then be determined which peripheral wishes to use the bus. Without a termination voltage bias, it would be difficult to determine which device is asserting a data bit because bits not being asserted would be floating. Other differential technologies may add a voltage bias at other locations on the bus, such as in conjunction with a driver or a receiver, or at a separate location.
However, adding a voltage bias (such as external fail-safe resistors) that creates a DC offset on a differential bus line tends to unbalance the symmetrical differential output drive current and also degrades signal quality. One problem is that this DC offset represents a DC noise source that can distort high speed data signals resulting in errors by the receiver. These errors are especially pronounced when the bus is operated at high speed due to the attenuation of the received AC data signal caused by long cables and high frequency operation.
Thus, while a bias voltage may be desirable to enter a known signaling state when a driver is not driving, it is undesirable when the bus is used for high speed data transfer. Another difficulty with the voltage bias is that it is invariant with signaling frequency and cable lengths, whereas these same factors adversely effect signals. Many existing designs use simple fixed termination voltage sources that are located at the end of the bus. Ultimately, with such a fixed voltage bias, an increase in signal frequency and/or cable length results in the signal becoming attenuated such that is cannot overcome the effect of the fixed voltage bias. In many cases the ends of the bus are not close to an intelligent device which might be able to alter the voltage bias value according to the traffic situation on the bus. Thus, although such termination voltage sources might be switched or altered with some knowledge of data frequency, no means of sending a signal is available. Furthermore, a determination of data frequency and direct manipulation of the voltage bias is rather complex, and in many bus designs there is not an extra signal line available for this type of control. In particular, in an SCSI bus there are no extra signal lines available for sending information to a termination bias voltage located at the end of a cable.
In previous single-ended and differential bus designs, the driver current or voltage swing is relatively large compared to the voltage bias, thus allowing significant cable length at the maximum operating frequency. This large swing (associated with high voltage differential designs) allows a bus to run at higher speeds and with longer cables than were originally specified. More recently though, low voltage differential signaling is seen as having advantages over high voltage differential signaling. Because of the higher power required with a high-voltage driver, power dissipation is an issue and two or three integrated circuits may be needed to implement a bus interface. In other words, not all of the bus signals can be implemented on one chip because of power concerns, so more chips are needed to help dissipate the power. Unfortunately, the use of more than one chip to implement a bus interface leads to mismatch and timing skew between the chips. On the other hand, the use of low voltage differential drivers saves power and allows all drivers and/or receivers for a bus to be integrated on one chip. Having all drivers or receivers on one chip avoids mismatch and skew problems and is simpler to integrate into a greater circuit.
A detailed description of a low voltage differential technology and its advantages and applications may be found in the "LVDS Owner's Manual and Design Guide" available from National Semiconductor Corporation of Sunnyvale, California, Literature No. 550062-001, 1997, which is hereby incorporated by reference. Such a low voltage differential signaling technology and other types is referred to as LVDS. LVDS uses a low voltage swing (about 350mV) to transmit information over a differential pair. The low voltage swing and current mode driver outputs of LVDS create low noise and provide a very low power consumption across frequency.
However, the use of a low voltage differential bus encounters problems with a voltage bias (such as external fail-safe resistors, whether in a terminator or other location on the bus). With a low voltage differential bus, the driver swing is chosen to be smaller (than previous single-ended or high voltage differential designs) so as to reduce attendant electromagnetic interference and driver chip power consumption. Although asymmetrical drivers are specified to compensate for the voltage bias, the values chosen for these asymmetrical drivers unnecessarily limit both the cable length and the signal margin at the receiver to unattractive values. At present, no conventional alternative is available to allow greater speed for longer cable lengths if the same fixed voltage bias is employed.
One method of using an asymmetrical output driver to compensate for the DC offset produced by the bias voltage is described in the draft document X3Y10 SCSI SPI-2 available from the ANSI X3T10 standards committee. An asymmetrical driver drives more current in the direction opposite to the voltage bias with the intent that the extra current in this direction cancel out the voltage bias. Since more current is driven in one state (iLe., asserted or negated) the driver is termed an asymmetrical driver. Unfortunately, the use of asymmetrical drivers on a differential signaling line (such as in LVDS) present numerous problems.
A first problem is that an asymmetrical driver generates greater power supply noise. This noise is cause by switching between the two different currents used to drive the two states on a differential line. When switching between the two different currents, the change in current over time (dI/dT) on the power supply lines along with any inherent inductance will generate greater noise.
A second problem is that unequal output currents creates greater radio frequency interference and electromagnetic interference.
A third problem resulting from an asymmetrical driver is the so-called "wedge" effect that causes phase distortion and eventual failure of differential signals to cross. The problem is due to the driver turning on in an AC mode and trying to cancel the voltage bias that is a constant DC value. Canceling a DC value with an AC source does not work well because the corrective effect with AC varies with frequency. As the frequency increases the correction of the asymmetrical drive is diminished due to loss in the cable, but the DC bias is not. This results in timing distortion of the recovered signal. In SCSI using LVDS technology, timing is critical and this phase distortion presents problems. Furthermore, at higher frequencies the two differential signals become forced apart, almost as if a wedge were being driven between the two of them. This "wedge" is a surprise to system designers and as it becomes more pronounced at higher frequencies, the two differential signals become farther and farther apart as they become attenuated and a receiver will eventually be unable to detect a signal change.
As an example of the "wedge" effect, consider a differential pair having an offset of 100mV and a zero-to-peak voltage of 100mV seen at each of the two receiver inputs. (Such a zero-to-peak voltage of 100mV may result at a receiver if a cable with a 6 dB loss is driven with a 400mV peak-to-peak signal). Assuming that a square wave (having a 50/50 duty cycle) is initially driven into the cable at a high enough frequency (such as 40 MHz), the resulting wave at the receiver resembles a sine wave more than a square wave. When a receiver receives such a sine wave while trying to detect a square wave signal the signal becomes distorted by 16% (42.5/57.5 duty cycle). Furthermore, should the offset between the two lines go to 125mV, then the duty cycle may become distorted by as much as 40%. Such a phase distortion causes timing problems with LVDS technology in particular, and is unacceptable for a SCSI bus at high frequencies and longer cable lengths.
A fourth problem is that an asymmetrical driver can never be perfect and will always have a difference between the assertion and negation levels. In a multi-drop bus system, the impedance of a signal line may change as more receivers and/or devices are added to the line. This impedance change effects the asymmetrical drive levels such that they no longer compensate exactly for the voltage bias value. Thus, the voltage bias value changes or the transmission line impedance changes, resulting in a lessening of the noise margin. For example, assuming a differential pair having a 100mV offset between the two lines, a termination resistance of 100 ohms, and a loaded cable having a loaded impedance of 70 ohms, because of the difference due to the impedance, there may be a difference in the actual asserted and negated voltage values by as much as 15%. Due to this variation of the termination voltage bias and the impedance of the transmission line, there will always be an asymmetrical waveform unless the design values for the difference current exactly match the real loaded cable and the bias being used. As such an exact match is difficult to achieve, such an asymmetrical driver can never guarantee resulting assertion and negation voltage levels that are the same. Furthermore, higher loading that further reduces the cable impedance can cause even more degradation of the signal. These losses occur before any cable transmission losses are taken into account, and before any losses associated with a receiver are taken into account.
A fifth problem with an asymmetrical driver is that circuitry to supply the extra current in one direction can cause the output capacitance to be different for driving one logic state or the other. Such circuitry typically includes a boost transistor connected through a boost resistor to a power source that is used to source the extra current needed to the positive output of the driver, and a corresponding boost transistor connected through a boost resistor to ground used to sink extra current from the minus output of the driver. Each of these boost transistors only turns on to drive a logic "one", and not when driving a logic "zero". Thus, the output capacitance on the node between the boost transistor and the boost resistor is only applied to an output when driving a particular logic state. Such a difference in the output capacitance for different logic states being driven causes excess noise because of the modulation of the output capacitance.
A sixth problem associated with an asymmetrical driver is that for current mode outputs, extra care or extra power consumption is needed to avoid switching noise being coupled into the bias circuitry. For example, when the differential transistors in an asymmetrical driver switch on and off (creating an approximate 1 volt swing) parasitic capacitors associated with these differential transistors and the current mirror transistors couple this switching noise on to the N-channel and P-channel bias nodes. This extra charge on the bias nodes changes the current through the current mirror transistors, thus generating noise in the output. Thus, with an asymmetrical driver having current mode outputs, the extra switching generates noise in the output.
A seventh problem with an asymmetrical driver is that as more output current is needed to drive in one direction, a different output impedance is created for driving a logic level "one" as opposed to a logic level "zero". Thus, the transmission line becomes modulated due to the different impedance. With a longer bus, and greater attenuation of signal strength, the noise generated by this modulation is a problem and may result in a receiver not being able to differentiate a signal from the noise.
An eighth problem with an asymmetrical driver is the asymmetric voltage swing received by a receiver. Although a larger peak-to-peak voltage swing may be achieved with an asymmetric driver, any extra voltage is not only wasted, but ends up causing more noise. For example, FIG. 1 shows a graph 10 having a vertical axis 12 representing 100mV per division and a horizontal axis 14 representing time. A plot of signal 16 is representative of a signal received by a receiver on one differential line that has been driven by an asymmetrical driver at a frequency of approximately 82 MHz. As can be seen from the plot, signal 16 reaches a low level of approximately 220mV and a high level of approximately 290mV. Thus, the peak-to-peak swing is approximately 510mV which is more than sufficient for signal differentiation by a receiver on a differential line. However, note that the high level of 290mV is asymmetric with respect to the low level of 220mV. The extra 70mV for the signal high level will cause extra noise on the transmission line because of the higher voltage.
A ninth problem with asymmetrical drivers is that the drivers must match the bias voltage, which itself may be inaccurate. For example, if a voltage source for the voltage bias or any of the termination resistors are out of tolerance, then there may not be exactly the expected differential between a pair of signals. A driver expecting an exact termination bias voltage of 100 mV may experience problems when driving asymmetrically if a particular expected termination bias voltage is out of tolerance.
Thus, it should be apparent that the use of an asymmetrical driver causes numerous problems that are accentuated at long cable lengths and high frequencies, and especially with LVDS.
Therefore, it would be desirable to be able use a symmetrical driver with differential signaling, thus allowing greater cable lengths and/or higher frequencies and/or better signal to noise ratios for high speed data transmission. It would also be desirable for such a technique to co-exist with existing differential signaling that does use a voltage bias so that cables and other technology currently in use can continue to be employed, so that a bus signal line is still able to achieve a known state when a driver is not driving, and so that fail-safe features may continue to be employed.